Whisper is a RISCV instruction set simulator (ISS) developed for the verification of the Swerv micro-controller. It allows the user to run RISCV code without RISCV hardware. It has an interactive mode where the user can single step the target RISCV code and inspect/modify the RISCV registers or the simulated system memory. It can also run in lock step with a Verilog simulator serving as a “golden model” against which an implementation is checked after each instruction of a test program. Official reference can be found here.


You can configure debugging tool using debug_tool option in “platformio.ini” (Project Configuration File):

platform = ...
board = ...
debug_tool = whisper

More options:


Name Description
CHIPS Alliance The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs.


Name Description
FreeRTOS FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 40 microcontroller platforms
WD-Firmware The WD Firmware package contains firmware applications and Processor Support Package (PSP) for various cores, alongside demos which support all features
Zephyr RTOS The Zephyr Project is a scalable real-time operating system (RTOS) supporting multiple hardware architectures, optimized for resource constrained devices, and built with safety and security in mind



For more detailed board information please scroll tables below by horizontal.

Name Platform Debug MCU Frequency Flash RAM
RVfpga: Digilent Nexys A7 CHIPS Alliance On-board   320MHz 16MB 1.16MB