Whisper is a RISCV instruction set simulator (ISS) developed for the verification of the Swerv micro-controller. It allows the user to run RISCV code without RISCV hardware. It has an interactive mode where the user can single step the target RISCV code and inspect/modify the RISCV registers or the simulated system memory. It can also run in lock step with a Verilog simulator serving as a “golden model” against which an implementation is checked after each instruction of a test program. Official reference can be found here.
[env:myenv] platform = ... board = ... debug_tool = whisper
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