Verilator is a free and open-source software tool which converts Verilog to a cycle-accurate behavioral model in C++ or SystemC. Official reference can be found here.
[env:myenv] platform = ... board = ... debug_tool = verilator
|CHIPS Alliance||The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs.|
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|WD-Firmware||The WD Firmware package contains firmware applications and Processor Support Package (PSP) for various cores, alongside demos which support all features|