GAPuino GAP8

Hardware

Platform RISC-V GAP: GreenWaves GAP8 IoT application processor enables the cost-effective development, deployment and autonomous operation of intelligent sensing devices that capture, analyze, classify and act on the fusion of rich data sources such as images, sounds or vibrations.

Microcontroller GAP8
Frequency 250MHz
Flash 64MB
RAM 8MB
Vendor GreenWaves Technologies

Configuration

Please use gapuino ID for board option in “platformio.ini” (Project Configuration File):

[env:gapuino]
platform = riscv_gap
board = gapuino

You can override default GAPuino GAP8 settings per build environment using board_*** option, where *** is a JSON object path from board manifest gapuino.json. For example, board_build.mcu, board_build.f_cpu, etc.

[env:gapuino]
platform = riscv_gap
board = gapuino

; change microcontroller
board_build.mcu = gap8

; change MCU frequency
board_build.f_cpu = 250000000L

Debugging

PIO Unified Debugger - “1-click” solution for debugging with a zero configuration.

Warning

You will need to install debug tool drivers depending on your system. Please click on compatible debug tool below for the further instructions and configuration information.

You can switch between debugging Tools & Debug Probes using debug_tool option in “platformio.ini” (Project Configuration File).

GAPuino GAP8 has on-board debug probe and IS READY for debugging. You don’t need to use/buy external debug probe.

Compatible Tools On-board Default
FTDI Chip Yes Yes

Frameworks

Name Description
mbed The mbed framework The mbed SDK has been designed to provide enough hardware abstraction to be intuitive and concise, yet powerful enough to build complex projects. It is built on the low-level ARM CMSIS APIs, allowing you to code down to the metal if needed. In addition to RTOS, USB and Networking libraries, a cookbook of hundreds of reusable peripheral and module libraries have been built on top of the SDK by the mbed Developer Community.
PULP OS PULP is a silicon-proven Parallel Ultra Low Power platform targeting high energy efficiencies. The platform is organized in clusters of RISC-V cores that share a tightly-coupled data memory.