Platform RISC-V: RISC-V is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
[env:coreplexip-e51-arty] platform = riscv board = coreplexip-e51-arty
You can override default E51 Arty (Artix-7) FPGA Dev Kit settings per build environment using
board_*** option, where
*** is a JSON object path from
board manifest coreplexip-e51-arty.json. For example,
[env:coreplexip-e51-arty] platform = riscv board = coreplexip-e51-arty ; change microcontroller board_build.mcu = e51 ; change MCU frequency board_build.f_cpu = 1500000000L
PIO Unified Debugger - “1-click” solution for debugging with a zero configuration.
You will need to install debug tool drivers depending on your system. Please click on compatible debug tool below for the further instructions and configuration information.
E51 Arty (Artix-7) FPGA Dev Kit does not have on-board debug probe and IS NOT READY for debugging. You will need to use/buy one of external probe listed below.